37 #define reg_i2c_set REG_ADDR32(0x00) 38 #define reg_i2c_speed REG_ADDR8(0x00) 39 #define reg_i2c_id REG_ADDR8(0x01) 45 #define reg_i2c_status REG_ADDR8(0x02) 52 #define reg_i2c_mode REG_ADDR8(0x03) 60 #define reg_i2c_adr_dat REG_ADDR16(0x04) 61 #define reg_i2c_dat_ctrl REG_ADDR32(0x04) 62 #define reg_i2c_di_ctrl REG_ADDR16(0x06) 63 #define reg_i2c_adr REG_ADDR8(0x04) 64 #define reg_i2c_do REG_ADDR8(0x05) 65 #define reg_i2c_di REG_ADDR8(0x06) 66 #define reg_i2c_ctrl REG_ADDR8(0x07) 78 #define reg_i2c_map_hadr REG_ADDR8(0xe0) 80 #define reg_i2c_slave_map_addrl REG_ADDR8(0xe1) 81 #define reg_i2c_slave_map_addrm REG_ADDR8(0xe2) 82 #define reg_i2c_slave_map_addrh REG_ADDR8(0xe3) 84 #define reg_i2c_slave_irq_status REG_ADDR8(0xe4) 85 #define reg_spi_slave_irq_status REG_ADDR8(0xe4) 86 #define reg_i2c_map_host_status REG_ADDR8(0xe4) 92 #define reg_i2c_map_read0 REG_ADDR8(0xe5) 93 #define reg_i2c_map_read1 REG_ADDR8(0xe6) 94 #define reg_i2c_map_read2 REG_ADDR8(0xe7) 98 #define reg_spi_data REG_ADDR8(0x08) 99 #define reg_spi_ctrl REG_ADDR8(0x09) 109 #define reg_spi_sp REG_ADDR8(0x0a) 115 #define reg_spi_inv_clk REG_ADDR8(0x0b) //spi supports four modes 122 #define reg_mspi_data REG_ADDR8(0x0c) 123 #define reg_mspi_ctrl REG_ADDR8(0x0d) 133 #define reg_mspi_mode REG_ADDR8(0x0f) 143 #define reg_rst0 REG_ADDR8(0x60) 154 #define reg_rst1 REG_ADDR8(0x61) 165 #define reg_rst2 REG_ADDR8(0x62) 177 #define reg_clk_en0 REG_ADDR8(0x63) 188 #define reg_clk_en1 REG_ADDR8(0x64) 199 #define reg_clk_en2 REG_ADDR8(0x65) 209 #define reg_clk_sel REG_ADDR8(0x66) 216 #define reg_i2s_step REG_ADDR8(0x67) 222 #define reg_i2s_mod REG_ADDR8(0x68) 225 #define reg_dmic_step REG_ADDR8(0x6c) 231 #define reg_dmic_mod REG_ADDR8(0x6d) 234 #define reg_wakeup_en REG_ADDR8(0x6e) 246 #define reg_pwdn_ctrl REG_ADDR8(0x6f) 254 #define reg_mcu_wakeup_mask REG_ADDR32(0x78) 258 #define reg_7816_clk_div REG_ADDR8(0x7b) 262 #define reg_uart_data_buf0 REG_ADDR8(0x90) 263 #define reg_uart_data_buf1 REG_ADDR8(0x91) 264 #define reg_uart_data_buf2 REG_ADDR8(0x92) 265 #define reg_uart_data_buf3 REG_ADDR8(0x93) 267 #define reg_uart_data_buf(i) REG_ADDR8(0x90 + (i)) //i = 0~3 268 #define reg_uart_clk_div REG_ADDR16(0x94) 274 #define reg_uart_ctrl0 REG_ADDR8(0x96) 283 #define reg_uart_ctrl1 REG_ADDR8(0x97) 294 #define reg_uart_ctrl2 REG_ADDR16(0x98) 306 #define reg_uart_ctrl3 REG_ADDR8(0x99) 312 #define reg_uart_rx_timeout0 REG_ADDR8(0x9a) 317 #define reg_uart_rx_timeout1 REG_ADDR8(0x9b) 326 #define reg_uart_buf_cnt REG_ADDR8(0x9c) 333 #define reg_uart_status0 REG_ADDR8(0x9d) 342 #define reg_uart_status1 REG_ADDR8(0x9e) 351 #define reg_uart_state REG_ADDR8(0x9f) 360 #define reg_swire_data REG_ADDR8(0xb0) 361 #define reg_swire_ctrl1 REG_ADDR8(0xb1) 370 #define reg_swire_clk_div REG_ADDR8(0xb2) 377 #define reg_swire_id REG_ADDR8(0xb3) 387 #define reg_ana_ctrl32 REG_ADDR32(0xb8) 388 #define reg_ana_addr_data REG_ADDR16(0xb8) 389 #define reg_ana_addr REG_ADDR8(0xb8) 390 #define reg_ana_data REG_ADDR8(0xb9) 391 #define reg_ana_ctrl REG_ADDR8(0xba) 404 #define reg_ctrl_ep_ptr REG_ADDR8(0x100) 405 #define reg_ctrl_ep_dat REG_ADDR8(0x101) 406 #define reg_ctrl_ep_ctrl REG_ADDR8(0x102) 415 #define reg_ctrl_ep_irq_sta REG_ADDR8(0x103) 424 #define reg_ctrl_ep_irq_mode REG_ADDR8(0x104) 436 #define reg_usb_ctrl REG_ADDR8(0x105) 444 #define reg_usb_cyc_cali REG_ADDR16(0x106) 445 #define reg_usb_mdev REG_ADDR8(0x10a) 446 #define reg_usb_host_conn REG_ADDR8(0x10b) 452 #define reg_usb_sups_cyc_cali REG_ADDR8(0x10c) 453 #define reg_usb_intf_alt REG_ADDR8(0x10d) 455 #define reg_usb_ep8123_ptr REG_ADDR32(0x110) 456 #define reg_usb_ep8_ptr REG_ADDR8(0x110) 457 #define reg_usb_ep1_ptr REG_ADDR8(0x111) 458 #define reg_usb_ep2_ptr REG_ADDR8(0x112) 459 #define reg_usb_ep3_ptr REG_ADDR8(0x113) 460 #define reg_usb_ep4567_ptr REG_ADDR32(0x114) 461 #define reg_usb_ep4_ptr REG_ADDR8(0x114) 462 #define reg_usb_ep5_ptr REG_ADDR8(0x115) 463 #define reg_usb_ep6_ptr REG_ADDR8(0x116) 464 #define reg_usb_ep7_ptr REG_ADDR8(0x117) 465 #define reg_usb_ep_ptr(i) REG_ADDR8(0x110+((i) & 0x07)) 467 #define reg_usb_ep8123_dat REG_ADDR32(0x118) 468 #define reg_usb_ep8_dat REG_ADDR8(0x118) 469 #define reg_usb_ep1_dat REG_ADDR8(0x119) 470 #define reg_usb_ep2_dat REG_ADDR8(0x11a) 471 #define reg_usb_ep3_dat REG_ADDR8(0x11b) 472 #define reg_usb_ep4567_dat REG_ADDR32(0x11c) 473 #define reg_usb_ep4_dat REG_ADDR8(0x11c) 474 #define reg_usb_ep5_dat REG_ADDR8(0x11d) 475 #define reg_usb_ep6_dat REG_ADDR8(0x11e) 476 #define reg_usb_ep7_dat REG_ADDR8(0x11f) 477 #define reg_usb_ep_dat(i) REG_ADDR8(0x118+((i) & 0x07)) 478 #define reg_usb_mic_dat0 REG_ADDR16(0x1800) 479 #define reg_usb_mic_dat1 REG_ADDR16(0x1802) 481 #define reg_usb_ep8_ctrl REG_ADDR8(0x120) 482 #define reg_usb_ep1_ctrl REG_ADDR8(0x121) 483 #define reg_usb_ep2_ctrl REG_ADDR8(0x122) 484 #define reg_usb_ep3_ctrl REG_ADDR8(0x123) 485 #define reg_usb_ep4_ctrl REG_ADDR8(0x124) 486 #define reg_usb_ep5_ctrl REG_ADDR8(0x125) 487 #define reg_usb_ep6_ctrl REG_ADDR8(0x126) 488 #define reg_usb_ep7_ctrl REG_ADDR8(0x127) 489 #define reg_usb_ep_ctrl(i) REG_ADDR8(0x120+((i) & 0x07)) 500 #define reg_usb_ep8123_buf_addr REG_ADDR32(0x128) 501 #define reg_usb_ep8_buf_addr REG_ADDR8(0x128) 502 #define reg_usb_ep1_buf_addr REG_ADDR8(0x129) 503 #define reg_usb_ep2_buf_addr REG_ADDR8(0x12a) 504 #define reg_usb_ep3_buf_addr REG_ADDR8(0x12b) 505 #define reg_usb_ep4567_buf_addr REG_ADDR32(0x12c) 506 #define reg_usb_ep4_buf_addr REG_ADDR8(0x12c) 507 #define reg_usb_ep5_buf_addr REG_ADDR8(0x12d) 508 #define reg_usb_ep6_buf_addr REG_ADDR8(0x12e) 509 #define reg_usb_ep7_buf_addr REG_ADDR8(0x12f) 510 #define reg_usb_ep_buf_addr(i) REG_ADDR8(0x128+((i) & 0x07)) 512 #define reg_usb_ram_ctrl REG_ADDR8(0x130) 520 #define reg_usb_iso_mode REG_ADDR8(0x138) 521 #define reg_usb_irq REG_ADDR8(0x139) 522 #define reg_usb_mask REG_ADDR8(0x13a) 533 #define reg_usb_ep8_send_max REG_ADDR8(0x13b) 534 #define reg_usb_ep8_send_thre REG_ADDR8(0x13c) 535 #define reg_usb_ep8_fifo_mode REG_ADDR8(0x13d) 536 #define reg_usb_ep_max_size REG_ADDR8(0x13e) 543 #define reg_rf_acc_len REG_ADDR8(0x405) 553 #define reg_rf_timestamp REG_ADDR32(0x450) 558 #define reg_aes_ctrl REG_ADDR8(0x540) 566 #define reg_aes_data REG_ADDR32(0x548) 567 #define reg_aes_key(v) REG_ADDR8(0x550+v) 572 #define reg_audio_ctrl REG_ADDR8(0x560) 585 #define reg_pwm_ctrl REG_ADDR8(0x563) 594 #define reg_ascl_tune REG_ADDR32(0x564) 596 #define reg_pn1_left REG_ADDR8(0x568) 603 #define reg_pn2_left REG_ADDR8(0x569) 610 #define reg_pn1_right REG_ADDR8(0x56a) 617 #define reg_pn2_right REG_ADDR8(0x56b) 626 #define reg_gpio_pa_in REG_ADDR8(0x580) 627 #define reg_gpio_pa_ie REG_ADDR8(0x581) 628 #define reg_gpio_pa_oen REG_ADDR8(0x582) 629 #define reg_gpio_pa_out REG_ADDR8(0x583) 630 #define reg_gpio_pa_pol REG_ADDR8(0x584) 631 #define reg_gpio_pa_ds REG_ADDR8(0x585) 632 #define reg_gpio_pa_gpio REG_ADDR8(0x586) 633 #define reg_gpio_pa_irq_en REG_ADDR8(0x587) 635 #define reg_gpio_pb_in REG_ADDR8(0x588) 636 #define areg_gpio_pb_ie 0xbd 637 #define reg_gpio_pb_oen REG_ADDR8(0x58a) 638 #define reg_gpio_pb_out REG_ADDR8(0x58b) 639 #define reg_gpio_pb_pol REG_ADDR8(0x58c) 640 #define areg_gpio_pb_ds 0xbf 641 #define reg_gpio_pb_gpio REG_ADDR8(0x58e) 642 #define reg_gpio_pb_irq_en REG_ADDR8(0x58f) 644 #define reg_gpio_pc_in REG_ADDR8(0x590) 645 #define areg_gpio_pc_ie 0xc0 646 #define reg_gpio_pc_oen REG_ADDR8(0x592) 647 #define reg_gpio_pc_out REG_ADDR8(0x593) 648 #define reg_gpio_pc_pol REG_ADDR8(0x594) 649 #define areg_gpio_pc_ds 0xc2 650 #define reg_gpio_pc_gpio REG_ADDR8(0x596) 651 #define reg_gpio_pc_irq_en REG_ADDR8(0x597) 653 #define reg_gpio_pd_in REG_ADDR8(0x598) 654 #define reg_gpio_pd_ie REG_ADDR8(0x599) 655 #define reg_gpio_pd_oen REG_ADDR8(0x59a) 656 #define reg_gpio_pd_out REG_ADDR8(0x59b) 657 #define reg_gpio_pd_pol REG_ADDR8(0x59c) 658 #define reg_gpio_pd_ds REG_ADDR8(0x59d) 659 #define reg_gpio_pd_gpio REG_ADDR8(0x59e) 660 #define reg_gpio_pd_irq_en REG_ADDR8(0x59f) 662 #define reg_gpio_pe_in REG_ADDR8(0x5a0) 663 #define reg_gpio_pe_ie REG_ADDR8(0x5a1) 664 #define reg_gpio_pe_oen REG_ADDR8(0x5a2) 665 #define reg_gpio_pe_out REG_ADDR8(0x5a3) 666 #define reg_gpio_pe_pol REG_ADDR8(0x5a4) 667 #define reg_gpio_pe_ds REG_ADDR8(0x5a5) 668 #define reg_gpio_pe_gpio REG_ADDR8(0x5a6) 669 #define reg_gpio_pe_irq_en REG_ADDR8(0x5a7) 671 #define reg_gpio_pa_setting1 REG_ADDR32(0x580) 672 #define reg_gpio_pa_setting2 REG_ADDR32(0x584) 673 #define reg_gpio_pd_setting1 REG_ADDR32(0x598) 674 #define reg_gpio_pd_setting2 REG_ADDR32(0x59c) 676 #define reg_gpio_in(i) REG_ADDR8(0x580+((i>>8)<<3)) 677 #define reg_gpio_ie(i) REG_ADDR8(0x581+((i>>8)<<3)) 678 #define reg_gpio_oen(i) REG_ADDR8(0x582+((i>>8)<<3)) 679 #define reg_gpio_out(i) REG_ADDR8(0x583+((i>>8)<<3)) 680 #define reg_gpio_pol(i) REG_ADDR8(0x584+((i>>8)<<3)) 681 #define reg_gpio_ds(i) REG_ADDR8(0x585+((i>>8)<<3)) 684 #define reg_gpio_func(i) REG_ADDR8(0x586+((i>>8)<<3)) 686 #define reg_gpio_irq_wakeup_en(i) REG_ADDR8(0x587+((i>>8)<<3)) // reg_irq_mask: FLD_IRQ_GPIO_EN 688 #define reg_gpio_irq_risc0_en(i) REG_ADDR8(0x5b8 + (i >> 8)) // reg_irq_mask: FLD_IRQ_GPIO_RISC0_EN 689 #define reg_gpio_irq_risc1_en(i) REG_ADDR8(0x5c0 + (i >> 8)) // reg_irq_mask: FLD_IRQ_GPIO_RISC1_EN 690 #define reg_gpio_irq_risc2_en(i) REG_ADDR8(0x5c8 + (i >> 8)) 692 #define reg_mux_func_a1 REG_ADDR8(0x5a8) 693 #define reg_mux_func_a2 REG_ADDR8(0x5a9) 694 #define reg_mux_func_b1 REG_ADDR8(0x5aa) 695 #define reg_mux_func_b2 REG_ADDR8(0x5ab) 696 #define reg_mux_func_c1 REG_ADDR8(0x5ac) 697 #define reg_mux_func_c2 REG_ADDR8(0x5ad) 698 #define reg_mux_func_d1 REG_ADDR8(0x5ae) 699 #define reg_mux_func_d2 REG_ADDR8(0x5af) 701 #define reg_gpio_wakeup_irq REG_ADDR8(0x5b5) 707 #define reg_pin_i2c_spi_out_en REG_ADDR8(0x5b6) 715 #define reg_pin_i2c_spi_en REG_ADDR8(0x5b7) //poweron default 0xff 730 #define reg_tmr_ctrl REG_ADDR32(0x620) 731 #define reg_tmr_ctrl16 REG_ADDR16(0x620) 732 #define reg_tmr_ctrl8 REG_ADDR8(0x620) 748 #define reg_tmr_sta REG_ADDR8(0x623) 756 #define reg_tmr0_capt REG_ADDR32(0x624) 757 #define reg_tmr1_capt REG_ADDR32(0x628) 758 #define reg_tmr2_capt REG_ADDR32(0x62c) 759 #define reg_tmr_capt(i) REG_ADDR32(0x624 + ((i) << 2)) 760 #define reg_tmr0_tick REG_ADDR32(0x630) 761 #define reg_tmr1_tick REG_ADDR32(0x634) 762 #define reg_tmr2_tick REG_ADDR32(0x638) 763 #define reg_tmr_tick(i) REG_ADDR32(0x630 + ((i) << 2)) 767 #define reg_irq_mask REG_ADDR32(0x640) 768 #define reg_irq_pri REG_ADDR32(0x644) 769 #define reg_irq_src REG_ADDR32(0x648) 770 #define reg_irq_src3 REG_ADDR8(0x64a) 802 #define reg_irq_en REG_ADDR8(0x643) 809 #define reg_system_tick REG_ADDR32(0x740) 810 #define reg_system_tick_irq REG_ADDR32(0x744) 811 #define reg_system_wakeup_tick REG_ADDR32(0x748) 812 #define reg_system_tick_mode REG_ADDR8(0x74c) 813 #define reg_system_tick_ctrl REG_ADDR8(0x74f) 827 #define reg_pwm_enable REG_ADDR8(0x780) 828 #define reg_pwm0_enable REG_ADDR8(0x781) 829 #define reg_pwm_clk REG_ADDR8(0x782) 831 #define reg_pwm0_mode REG_ADDR8(0x783) 834 #define reg_pwm_invert REG_ADDR8(0x784) 835 #define reg_pwm_n_invert REG_ADDR8(0x785) 836 #define reg_pwm_pol REG_ADDR8(0x786) 838 #define reg_pwm_cycle(i) REG_ADDR32(0x794 + (i << 2)) //<15:0>: TCMP 0~5 <31:16>: TMAX 0~5 839 #define reg_pwm_cmp(i) REG_ADDR16(0x794 + (i << 2)) //TCMP 0~5 840 #define reg_pwm_max(i) REG_ADDR16(0x796 + (i << 2)) //TMAX 0~5 846 #define reg_pwm0_pulse_num REG_ADDR16(0x7ac) 848 #define reg_pwm_irq_mask REG_ADDR8(0x7b0) 849 #define reg_pwm_irq_sta REG_ADDR8(0x7b1) 863 #define reg_pwm0_fifo_mode_irq_mask REG_ADDR8(0x7b2) 869 #define reg_pwm0_fifo_mode_irq_sta REG_ADDR8(0x7b3) 877 #define reg_pwm_tcmp0_shadow REG_ADDR16(0x7c4) //<15:0>: TCMP 0~5 <31:16>: TMAX 0~5 878 #define reg_pwm_tmax0_shadow REG_ADDR16(0x7c6) //TCMP 0~5 880 #define reg_pwm_ir_fifo_dat(i) REG_ADDR16(0x7c8+i*2) 881 #define reg_pwm_ir_fifo_irq_trig_level REG_ADDR8(0x7cc) 883 #define reg_pwm_ir_fifo_data_status REG_ADDR8(0x7cd) 890 #define reg_pwm_ir_clr_fifo_data REG_ADDR8(0x7ce) 898 #define reg_fifo0_data REG_ADDR32(0x800) 899 #define reg_fifo1_data REG_ADDR32(0x900) 900 #define reg_fifo2_data REG_ADDR32(0xa00) 904 #define reg_dfifo0_addr REG_ADDR16(0xb00) 905 #define reg_dfifo0_size REG_ADDR8(0xb02) 906 #define reg_dfifo0_addHi REG_ADDR8(0xb03) //default 0x04, no need set 908 #define reg_dfifo1_addr REG_ADDR16(0xb04) 909 #define reg_dfifo1_size REG_ADDR8(0xb06) 910 #define reg_dfifo1_addHi REG_ADDR8(0xb07) //default 0x04, no need set 913 #define reg_dfifo2_addr REG_ADDR16(0xb08) 914 #define reg_dfifo2_size REG_ADDR8(0xb0a) 915 #define reg_dfifo2_addHi REG_ADDR8(0xb0b) //default 0x04, no need set 917 #define reg_dfifo_audio_addr reg_dfifo0_addr 918 #define reg_dfifo_audio_size reg_dfifo0_size 920 #define reg_dfifo_misc_chn_addr reg_dfifo2_addr 921 #define reg_dfifo_misc_chn_size reg_dfifo2_size 924 #define reg_dfifo0_l_level REG_ADDR8(0xb0c) //dfifo0 low int threshold(wptr - rptr) 925 #define reg_dfifo0_h_level REG_ADDR8(0xb0d) //dfifo0 high int threshold(wptr - rptr) 926 #define reg_dfifo1_h_level REG_ADDR8(0xb0e) //dfifo1 high int threshold(wptr - rptr) 927 #define reg_dfifo2_h_level REG_ADDR8(0xb0f) //dfifo2 high int threshold(wptr - rptr) 930 #define reg_dfifo_mode REG_ADDR8(0xb10) 942 #define reg_dfifo_ain REG_ADDR8(0xb11) 968 #define reg_dfifo_dec_ratio REG_ADDR8(0xb12) 970 #define reg_dfifo_irq_status REG_ADDR8(0xb13) 977 #define reg_dfifo0_rptr REG_ADDR16(0xb14) 978 #define reg_dfifo0_wptr REG_ADDR16(0xb16) 980 #define reg_dfifo1_rptr REG_ADDR16(0xb18) 981 #define reg_dfifo1_wptr REG_ADDR16(0xb1a) 983 #define reg_dfifo2_rptr REG_ADDR16(0xb1c) 984 #define reg_dfifo2_wptr REG_ADDR16(0xb1e) 987 #define reg_audio_wptr reg_dfifo0_wptr 989 #define reg_dfifo0_num REG_ADDR16(0xb20) 990 #define reg_dfifo1_num REG_ADDR16(0xb24) 991 #define reg_dfifo2_num REG_ADDR16(0xb28) 993 #define reg_dfifo0_manual REG_ADDR8(0xb2c) 998 #define reg_dfifo0_man_dat REG_ADDR32(0xb30) 1000 #define reg_alc_sft REG_ADDR8(0xb34) 1002 #define reg_audio_dec_mode REG_ADDR8(0xb35) 1009 #define reg_adc_mul REG_ADDR8(0xb36) 1010 #define reg_adc_bias REG_ADDR8(0xb37) 1012 #define reg_aud_alc_hpf_lpf_ctrl REG_ADDR8(0xb40) 1023 #define reg_aud_alc_vol_l_chn REG_ADDR8(0xb41) //default 0x00, will be 0x20 after ana_34 set to 0x80 1024 #define reg_aud_alc_vol_r_chn REG_ADDR8(0xb42) //default 0x00, will be 0x20 after ana_34 set to 0x80 1033 #define reg_alc_vol_h REG_ADDR8(0xb43) 1040 #define reg_alc_vol_th_h REG_ADDR16(0xb44) 1041 #define reg_alc_vol_th_l REG_ADDR16(0xb46) 1042 #define reg_alc_vol_thn REG_ADDR16(0xb48) 1043 #define reg_alc_vad_thn REG_ADDR16(0xb4a) 1045 #define reg_alc_vol_step REG_ADDR8(0xb4c) 1047 #define reg_alc_vol_l REG_ADDR8(0xb4d) 1048 #define reg_alc_vol_r REG_ADDR8(0xb4e) 1050 #define reg_alc_peak_tick REG_ADDR16(0xb50) 1052 #define reg_alc_dec_tick REG_ADDR8(0xb52) 1053 #define reg_alc_noi_tick REG_ADDR8(0xb53) 1056 #define reg_aud_alc_cfg REG_ADDR8(0xb54) //default 0x00, will be 0x02 after ana_34 set to 0x80 1062 #define reg_alc_coef_iir REG_ADDR8(0xb55) 1063 #define reg_alc_dat_mask REG_ADDR8(0xb56) 1064 #define reg_alc_inc_spd REG_ADDR8(0xb57) 1065 #define reg_alc_inc_max REG_ADDR8(0xb58) 1066 #define reg_alc_dec_spd REG_ADDR8(0xb59) 1067 #define reg_alc_dec_max REG_ADDR8(0xb5a) 1068 #define reg_alc_noi_spd REG_ADDR8(0xb5b) 1069 #define reg_alc_noi_max REG_ADDR8(0xb5c) 1071 #define reg_pga_gain_init REG_ADDR8(0xb5d) 1072 #define reg_pga_gain_l REG_ADDR8(0xb5e) //used to check current left channel gain in analog mode auto regulate 1073 #define reg_pga_gain_r REG_ADDR8(0xb5f) //used to check current right channel gain in analog mode auto regulate 1074 #define reg_pga_man_speed REG_ADDR8(0xb60) 1076 #define reg_pga_man_target_l REG_ADDR8(0xb61) 1077 #define reg_pga_value_l REG_ADDR8(0xb62) 1078 #define reg_pga_fix_value REG_ADDR8(0xb63) 1086 #define reg_pga_r_l REG_ADDR8(0xb64) 1087 #define reg_pga_man_target_r REG_ADDR8(0xb65) 1088 #define reg_pga_value_r REG_ADDR8(0xb66) 1093 #define reg_dma0_addr REG_ADDR16(0xc00) 1094 #define reg_dma0_size REG_ADDR8(0xc02) 1095 #define reg_dma0_mode REG_ADDR8(0xc03) 1107 #define reg_dma1_addr REG_ADDR16(0xc04) 1108 #define reg_dma1_size REG_ADDR8(0xc06) 1109 #define reg_dma1_mode REG_ADDR8(0xc07) 1112 #define reg_dma2_addr REG_ADDR16(0xc08) 1113 #define reg_dma2_size REG_ADDR8(0xc0a) 1114 #define reg_dma2_mode REG_ADDR8(0xc0b) 1117 #define reg_dma3_addr REG_ADDR16(0xc0c) 1118 #define reg_dma3_size REG_ADDR8(0xc0e) 1119 #define reg_dma3_mode REG_ADDR8(0xc0f) 1121 #define reg_dma4_addr REG_ADDR16(0xc10) 1122 #define reg_dma4_size REG_ADDR8(0xc12) 1123 #define reg_dma4_mode REG_ADDR8(0xc13) 1125 #define reg_dma5_addr REG_ADDR16(0xc14) 1126 #define reg_dma5_size REG_ADDR8(0xc16) 1127 #define reg_dma5_mode REG_ADDR8(0xc17) 1130 #define reg_dma7_addr REG_ADDR16(0xc18) 1131 #define reg_dma7_size REG_ADDR8(0xc1a) 1132 #define reg_dma7_mode REG_ADDR8(0xc1b) 1135 #define reg_dma_t_addr REG_ADDR16(0xc1c) 1136 #define reg_dma_t_size REG_ADDR8(0xc1e) 1138 #define reg_dma_size(v) REG_ADDR8(0xc02+4*v) 1141 #define reg_dma_uart_rx_addr reg_dma0_addr 1142 #define reg_dma_uart_rx_size reg_dma0_size 1143 #define reg_dma_uart_rx_mode reg_dma0_mode 1145 #define reg_dma_uart_tx_addr reg_dma1_addr 1146 #define reg_dma_uart_tx_size reg_dma1_size 1147 #define reg_dma_uart_tx_mode reg_dma1_mode 1149 #define reg_dma_rf_rx_addr reg_dma2_addr 1150 #define reg_dma_rf_rx_size reg_dma2_size 1151 #define reg_dma_rf_rx_mode reg_dma2_mode 1153 #define reg_dma_rf_tx_addr reg_dma3_addr 1154 #define reg_dma_rf_tx_size reg_dma3_size 1155 #define reg_dma_rf_tx_mode reg_dma3_mode 1157 #define reg_dma_pwm_addr reg_dma7_addr 1158 #define reg_dma_pwm_size reg_dma7_size 1159 #define reg_dma_pwm_mode reg_dma7_mode 1163 #define reg_dma_chn_en REG_ADDR8(0xc20) 1164 #define reg_dma_chn_irq_msk REG_ADDR8(0xc21) 1165 #define reg_dma_tx_rdy0 REG_ADDR8(0xc24) 1166 #define reg_dma_tx_rdy1 REG_ADDR8(0xc25) 1167 #define reg_dma_rx_rdy0 REG_ADDR8(0xc26) 1168 #define reg_dma_rx_rdy1 REG_ADDR8(0xc27) 1170 #define reg_dma_irq_status reg_dma_rx_rdy0 1194 #define reg_dma_rx_rptr REG_ADDR8(0xc28) 1195 #define reg_dma_rx_wptr REG_ADDR8(0xc29) 1197 #define reg_dma_tx_rptr REG_ADDR8(0xc2a) 1198 #define reg_dma_tx_wptr REG_ADDR8(0xc2b) 1199 #define reg_dma_tx_fifo REG_ADDR16(0xc2c) 1206 #define reg_dma0_addrHi REG_ADDR8(0xc40) 1207 #define reg_dma1_addrHi REG_ADDR8(0xc41) 1208 #define reg_dma2_addrHi REG_ADDR8(0xc42) 1209 #define reg_dma3_addrHi REG_ADDR8(0xc43) 1210 #define reg_dma4_addrHi REG_ADDR8(0xc44) 1211 #define reg_dma5_addrHi REG_ADDR8(0xc45) 1212 #define reg_dma_ta_addrHi REG_ADDR8(0xc46) 1213 #define reg_dma_a3_addrHi REG_ADDR8(0xc47) 1214 #define reg_dma7_addrHi REG_ADDR8(0xc48) 1218 #define reg_rf_ll_ctrl_0 REG_ADDR8(0xf02) 1220 #define reg_rf_ll_ctrl_1 REG_ADDR8(0xf03) 1234 #define FSM_TIMEOUT_ENABLE ( reg_rf_ll_ctrl_1 |= FLD_RF_FSM_TIMEOUT_EN ) 1235 #define FSM_TIMEOUT_DISABLE ( reg_rf_ll_ctrl_1 &= (~FLD_RF_FSM_TIMEOUT_EN) ) 1237 #define reg_rf_rx_timeout REG_ADDR16(0xf0a) 1239 #define reg_rf_ll_ctrl_2 REG_ADDR8(0xf15) 1241 #define reg_rf_ll_ctrl_3 REG_ADDR8(0xf16) 1250 #define reg_rf_irq_mask REG_ADDR16(0xf1c) 1251 #define reg_rf_irq_status REG_ADDR16(0xf20) 1252 #define reg_rf_fsm_timeout REG_ADDR32(0xf2c) 1254 #define CLEAR_ALL_RFIRQ_STATUS ( reg_rf_irq_status = 0xffff ) 1281 #define areg_06_pll_bg 0x06 1286 #define areg_0e_pa0_pa3_pull 0x0E 1287 #define areg_0f_pa4_pa7_pull 0x0F 1288 #define areg_10_pb0_pb3_pull 0x10 1289 #define areg_11_pb4_pb7_pull 0x11 1290 #define areg_12_pc0_pc3_pull 0x12 1291 #define areg_13_pc4_pc7_pull 0x13 1292 #define areg_14_pd0_pd3_pull 0x14 1293 #define areg_15_pd4_pd7_pull 0x15 1296 #define areg_clk_setting 0x82 1305 #define areg_xo_setting 0x8a 1312 #if defined(__cplusplus) Definition: register_8258.h:539
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IRQ_DMAIrqTypeDef
Definition: register_8258.h:1182
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#define BIT(n)
Definition: bsp.h:33
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#define BIT_RNG(s, e)
Definition: bsp.h:35
Definition: register_8258.h:561
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