TLSR8258F512 embeds I2C hardware module, which could act as Master mode or Slave mode. I2C is a popular inter-IC interface requiring only 2 bus lines, a serial data line(SDA) and a serial clock line(SCL).
Telink I2C module supports standard-mode (100kbps) and fast-mode (400kbps) with restriction that system clock must be by at least 10x of data rate.
Two wires, SDA and SCL(SCK) carry information between Master device and Slave device connected to the bus. Each device is recognized by unique address(ID). Master device is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer.Slave device is the device addressed by a Master.
Both SDA and SCL are bidirectional lines connected to a positive supply voltage via a pull-up resister. When the bus is free, both lines are HIGH. It's noted that data in SDA line must keep stable when clock signal in SCL line is at high level, and level state in SDA line is only allowed to change when clock signal in SCL line is at low level.
In DMA mode, other Master devices could access (read/write) the specified address in digital register and SRAM of the TLSR8258F512 according to I2C protocol. I2C module of the TLSR8258f512 will execute the read/write command from I2C master device automatically.
It should be noted that compared to the previous chip series, the starting address of the sram of TLSR8258 starts from 0x840000, which means that if you want to access SRAM of TLSR8258, the length of the access address needs at least up to 3 bytes.
The I2C module of TLSR8258 support automatic address increment, which means that if you want to read or write a data byte of the specified length, you only need to send the address once.
The read and write format in DMA mode is as follows:
In Mapping mode, the master device can only read or write the address block(128-byte buffer) specified by the slave device. Regarding the 128-byte buffer definition and usage, there are the following precautions:
The read and write format in Mapping mode is as follows
I2C hardware and SPI hardware modules in the chip share part of the hardware, as a result, when both hardware interfaces are used, the restrictions listed within this section need to be taken into consideration.
In order to facilitate users to quickly develop products according to their own needs, TSI provide the following related APIs and examples.
| APIs list | Description | Example | Update Date | Status |
|---|---|---|---|---|
| reset_i2c_moudle() | reset the module of I2C | - | 2019-1-10 | Done |
| i2c_set_id() | set the id of slave device | - | 2019-1-10 | Done |
| i2c_gpio_set() | set pin of slave device or master device | API-I2C-CASE1 | 2019-1-10 | Done |
| i2c_master_init() | initiate master device(slave id and i2c clock) | API-I2C-CASE1 | 2019-1-10 | Done |
| i2c_slave_init() | initiate slave device(device id, slave mode and buffer) | API-I2C-CASE4 | 2019-1-10 | Done |
| i2c_write_byte() | write data by byte to slave device | - | 2019-1-10 | Done |
| i2c_read_byte() | read data by byte from slave device | - | 2019-1-10 | Done |
| i2c_write_series() | write a packet of data to slave device | API-I2C-CASE1 | 2019-1-10 | Done |
| i2c_read_series() | read a packet of data from slave device | API-I2C-CASE1 | 2019-1-10 | Done |
TSI provides the following examples of this module to help users quickly understand and apply related modules.
| Examples list | Description | Update Date | Status |
|---|---|---|---|
| API-I2C-CASE1 | I2C master in DMA mode | 2019-1-10 | Done |
| API-I2C-CASE2 | I2C slave in DMA mode | 2019-1-10 | Done |
| API-I2C-CASE3 | I2C master in Mapping mode | 2019-1-10 | Done |
| API-I2C-CASE4 | I2C slave in Mapping mode | 2019-1-10 | Done |
| Date | Description | Author |
|---|---|---|
| 2019-1-10 | initial release | LJW |
| 2019-8-15 | update api name for application | LJW |